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automotive power data sheet rev. 1.1, 2012-12-03 tle4291 low drop out linear voltage regulator TLE4291E
data sheet 2 rev. 1.1, 2012-12-03 tle4291 table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 description voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 electrical characteristics vo ltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 electrical characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 description enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 electrical characteristics enable functi on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1 description reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 electrical characteristics reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3 typical performance characteristics reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 electrical characteristics watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 typical performance characteristics standard watchdog fu nction . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
pg-ssop-14 ep type package marking TLE4291E pg-ssop-14 ep tle4291 data sheet 3 rev. 1.1, 2012-12-03 low drop out linear voltage regulator 5 v fixed output voltage TLE4291E 1overview features ? output voltage 5 v 2% ? output current up to 450 ma ? very low current consumption ? power-on and undervoltage reset with programmable delay time ? integrated standard watchdog ? reset low down to v q = 1 v ? very low dropout voltage ? output current limitation ? reverse polarity protection ? overtemperature protection ? suitable for use in automotive electronics ? wide temperature range from -40 c up to 150 c ? input voltage range from -42 v to 45 v ? green product (rohs compliant) ? aec qualified description the tle4291 is a monolithic integrated low-dropout voltage regulator in a pg-ssop-14 ep exposed pad package, especially designed for automo tive applications. an input voltage up to 42 v is regula ted to an output voltage of 5.0 v. the component is able to drive lo ads up to 450 ma. it is shor t-circuit protected by the implemented current limitation and has an integrated overtemperature shutdown. the integrated reset and watchdog function makes it suitable for supplying microprocessor systems in automotive environments. the watchdog and the power-on reset delay timing can be programmed by the external delay capacitor.
data sheet 4 rev. 1.1, 2012-12-03 tle4291 block diagram 2 block diagram figure 1 block diagram and simplified application circuit reset and watchdog generator bandgap reference protection circuits gnd d radj wi q wo ro c q c d load e. g. micro controller xc22xx gnd i supply regulated output voltage b lockd iagr am_a ppc ir cuit1.vsd tle 4291 en internal supply
tle4291 pin configuration data sheet 5 rev. 1.1, 2012-12-03 3 pin configuration 3.1 pin assignment figure 2 pin configuration pg-ssop-14 ep 3.2 pin definitions and functions 11 pin symbol function 1i regulator input and ic supply for compensating line influences, a capacitor to gnd close to the ic pins is recommended. 2en enable high signal enables the regulator; low signal disables the regulator; connect to i, if the enab le function is not needed. 3n.c. not connected internally not connected; connection to pcb gnd recommended. 4ro reset output open collector output with an internal pull-up resistor to the output q. an additional external pull-up resistor to the output q is optional. leave open if the reset function is not needed. 5n.c. not connected internally not connected; connection to pcb gnd recommended. 6radj reset switching threshold adjust for reset threshold adjustment connect to a voltage divider from output q to gnd. for triggering the reset at the internally determined threshold, connect this pin directly to gnd. connect directly to gnd if the reset function is not needed. 7gnd ground interconnect the gnd pins on pcb. connect to heat sink area. pg -ssop -14-1 .vsd iq en n.c. ro n.c. radj gnd n.c. wo n.c. wi n.c. d 1 2 3 4 5 6 7 14 13 12 11 10 9 8
data sheet 6 rev. 1.1, 2012-12-03 tle4291 pin configuration 8d reset delay and watchdog timing connect a ceramic capacitor d (pin 6) to gnd for reset delay and watchdog timing adjustment. leave only open if both, the reset and the watchdog function are not needed. 9n.c. not connected internally not connected; connection to pcb gnd recommended. 10 wi watchdog input positive edge triggered input, usab le for microcontroller monitoring. connect to gnd if the watchdog function is not needed. 11 n.c. not connected internally not connected; connection to pcb gnd recommended 12 wo watchdog output open collector output with an internal pull-up resistor to the output q. an additional external pull-up resistor to the output q is optional. leave open if the watchdog function is not needed. 13 n.c. not connected internally not connected; connection to pcb gnd recommended. 14 q 5 v regulator output block to gnd with a capacitor close to the ic pins, respecting capacitance and esr requirements given in the chapter 4.2 . pad heat sink connect to pcb heat sink area and gnd pin symbol function
tle4291 general product characteristics data sheet 7 rev. 1.1, 2012-12-03 4 general product characteristics 4.1 absolute maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 supply voltage v i -42 45 v ? 4.1.2 enable input en v en -42 45 v ? 4.1.3 regulator output v q -1 7 v ? 4.1.4 watchdog input v wi -0.3 7 v ? 4.1.5 watchdog output v wo -0.3 7 v ? 4.1.6 reset adjust v radj -0.3 7 v ? 4.1.7 reset output v ro -0.3 7 v ? 4.1.8 reset delay v d -0.3 7 v ? temperatures 4.1.9 junction temperature t j -40 150 c? 4.1.10 storage temperature t stg -55 150 c? esd susceptibility pg-ssop-14 ep 4.1.11 esd resistivity to gnd v esd -4 4 kv hbm 2) 2) esd susceptibility, hbm according to aec-q100-002-jesd 22-a114 4.1.12 esd resistivity to gnd v esd -750 750 v cdm 3) 3) esd susceptibility, charged device model ?cdm? esda stm5.3.1
data sheet 8 rev. 1.1, 2012-12-03 tle4291 general product characteristics 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . pos. parameter symbol limit values unit conditions min. max. 4.2.1 input voltage range for normal operation v i v q + v dr 42 v 1) 1) for specification of the output voltage v q and the drop out voltage v dr , see chapter 5 voltage regulator . 4.2.2 extended input voltage range v i 3.3 42 v 2) 2) the output voltage will follow the input volt age, but is outside the specified range. for details see chapter 5 voltage regulator . 4.2.3 junction temperature t j -40 150 c? 4.2.4 output capaci tor requirements c q 22 ? f 3) 3) the minimum output capacitance is applicable for a worst case capacitance tolerance of 30% 4.2.5 esr cq ?3 4) 4) relevant esr value at f = 10 khz pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case 1) 1) not subject to production test, specified by design. r thjc ?7?k/w? 4.3.2 junction to ambient 1) r thja ?43?k/w 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. 4.3.3 ? 120 ? k/w footprint only 3) 3) specified r thja value is according to jedec jesd 51-3 at nat ural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). 4.3.4 ? 59 ? k/w 300 mm 2 heatsink area on pcb 3) 4.3.5 ? 49 ? k/w 600 mm 2 heatsink area on pcb 3)
tle4291 voltage regulator data sheet 9 rev. 1.1, 2012-12-03 5 voltage regulator 5.1 description voltage regulator the output voltage v q is controlled by comparing a portion of it to an internal reference and driving a pnp pass transistor accordingly. saturation cont rol as a function of the load current prevents any oversaturation of the pass element. the control loop stability depends on the ou tput capacitor c q , the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. to ensure stable operation, the output capacitor?s capacitance and its equivalent series resist or esr requirements given in chapter 4.2 table ?functional range? have to be maintained. for details see also the typical perf ormance graph ?output capa citor series resistor esr cq vs. output current i q ?. also, the output capacitor shall be sized to buffer load transients. an input capacitor c i is not needed for the control loop stability, but recommended to bu ffer line influences. connect the capacitors close to the ic terminals. protection circuitry prevent the ic as well as the application fr om destruction in case of catastrophic events. these safeguards contain output curr ent limitation, reverse polarity protection as well as thermal shutdown in case of overtemperature. in order to avoid excessive power dissipation that coul d never be handled by the pass element and the package, the maximum output current is de creased at input voltages above v i = 28 v. the thermal shutdown circuit prevents the ic from imme diate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. after the chip has cooled down, the regulator restarts. this leads to an oscillatory behavior of the output volt age until the fault is remo ved. however, junction temperatures above 150 c are outside the maximum ratings a nd therefore reduce the ic lifetime. the tle4291 allows a negative supply voltage. however, se veral small currents are flowing into the ic increasing its junction temperature. th is has to be considered for the thermal desig n, respecting that the thermal protection circuit is not operating during reverse polarity condition. figure 3 block diagram voltage regulator circuit figure 4 output voltage vs. input voltage bandgap reference gnd q i b lockdiagram _v oltageregulator .vsd saturation control current limitation temperature shutdown c q load supply c i regulated output voltage i q i i v q + v i + v t diagram_output-inputvoltage.svg v q,nom v i v dr v q d v q d t i load c q d v q d t i q,max - i load c q v i(ext),min
data sheet 10 rev. 1.1, 2012-12-03 tle4291 voltage regulator 5.2 electrical character istics voltage regulator electrical characteristics: voltage regulator v i = 13.5v, t j = -40 c to +150 c, all voltages with respect to ground, di rection of currents as shown in figure 3 (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.2.1 output voltage v q 4.95.05.1v 1 ma < i q < 450 ma 9 v < v i < 28 v 5.2.2 output voltage v q 4.95.05.1v 1 ma < i q < 400 ma 6 v < v i < 28 v 5.2.3 output voltage v q 4.85 5.0 5.15 v 1 ma < i q < 200 ma 6 v < v i < 40 v 5.2.4 output current limitation i q,max 451 ? 1100 ma v q =4.8 v 5.2.5 load regulation steady-state d v q,load -30 -15 ? mv i q = 5 ma to 400 ma; v i = 8 v 5.2.6 line regulation steady-state d v q,line ?515mv v i = 8 v to 32 v; i q = 5 ma 5.2.7 power supply ripple rejection psrr 60 65 ? db f ripple = 100 hz; v ripple = 1 vpp 1) 1) parameter not subject to produ ction test; specified by design. 5.2.8 drop out voltage v dr = v i - v q v dr ? 120 250 mv i q = 100 ma 2) 2) measured when the output voltage v q has dropped 100 mv from its nominal value. 5.2.9 ? 250 500 mv i q = 300 ma 2) 5.2.10 overtemperature shutdown threshold t j,sd 151 ? 200 c t j increasing 1)
tle4291 voltage regulator data sheet 11 rev. 1.1, 2012-12-03 5.3 typical performance characteristics voltage regulator output voltage v q versus junction temperature t j output current i q versus input voltage v i output current i q versus input voltage v i output capacitor series resistor esr( c q ) versus output current i q 01_vq_tj.vsd 4.80 4.90 5.00 5.10 5.20 -40 0 40 80 120 160 t j [c] v q [v] v i = 7 v i q = 5 ma 0 100 200 300 400 500 600 700 800 900 1000 1100 2 2.5 3 3.5 4 4.5 5 v i [v] i q,max [ma] t j = -40c t j = 25c t j = 150c 03_iqmax_vi.vsd 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 v i [v] i q,maxq [ma] tj = -40 c tj = 25 c tj = 150 c 02_iqmax_vi.vsd 0.01 0.1 1 10 100 0 80 160 240 320 400 i q [ma] esr [ @ ] c q = 22 f t j = -40..150 c v i = 6v..28 v unstable region stable region 04_esr_iq.vsd
data sheet 12 rev. 1.1, 2012-12-03 tle4291 voltage regulator line regulation d v q,line versus input voltage change d v i dropout voltage v dr versus output current i q load regulation d v q,line versus output current change d i q power supply ripple rejection psrr 0 2 4 6 8 10 12 14 510152025303540 v i [v] dv q [mv] t j = -40c t j = 25c t j = 150c 05_dvq_vi.vsd 0 50 100 150 200 250 300 350 400 450 -40 0 40 80 120 160 t j [c] v dr [mv] i q = 100 ma i q = 300 ma i q = 400 ma 07_vdr_tj.vsd 06_dvq_iq.vsd -25 -20 -15 -10 -5 0 0 100 200 300 400 i q [ma] dv q [mv] t j = -40 c t j = 25 c t j = 150 c 0 10 20 30 40 50 60 70 80 90 freq [khz] psrr [db] 08_psrr_freq.vsd 0.01 0.1 1 10 100 1000 150c 25c -40c
tle4291 current consumption data sheet 13 rev. 1.1, 2012-12-03 6 current consumption 6.1 electrical characteris tics current consumption figure 5 parameter definition electrical characteristics: current consumption v i = 13.5v, t j = -40 c to +150 c, all voltages with respect to ground, di rections of currents as shown in figure 5 (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 6.1.1 current consumption i q,off = i i i q,off ?25 a v en = 0 v; t j 105 c 6.1.2 current consumption i q = i i - i q i q ? 220 300 a v en = 5v ; i q = 1ma; t j 85 c 6.1.3 ? ? 350 a v en = 5v ; i q = 1ma; t j 105 c 6.1.4 ? 6 15 ma v en = 5v ; i q = 250 ma 6.1.5 ? 16 30 ma v en = 5v ; i q = 400 ma gnd q i currentconsumption _ parameterdefinition .vsd c q load supply c i regulated output voltage i q i i v q + v i + i q voltage regulator v en + i en en
data sheet 14 rev. 1.1, 2012-12-03 tle4291 current consumption 6.2 typical performance charac teristics current consumption current consumption i q versus output current i q current consumption i q versus input voltage v i current consumption i q versus input voltage v i current consumption i q versus input voltage v i 0.0 5.0 10.0 15.0 20.0 25.0 0 50 100 150 200 250 300 350 400 i q [ma] i q [ma] t j = -40c t j = 25c t j = 150c 01_iq_iq.vsd 03_iq_lowvi_50k.vsd 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 012345678 v i [v] i q [ma] t=-40c t=25c t=150c i q = 100a 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 5 10 15 20 25 30 35 40 v i [v] i q [ma] 50ma 100a 02_iq_vi_50k_100ohm.vsd 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 012345678 v i [v] i q [ma] t=-40c t=25c t=150c 04_iq_lowvi_100ohm.vsd i q = 50ma
tle4291 current consumption data sheet 15 rev. 1.1, 2012-12-03 current consumption i q versus junction temperature t j regulator disabled 05_iq_tj_en=0.vsd 0.0 1.0 2.0 3.0 4.0 5.0 -40 0 40 80 120 t j [c] i q [ua]
data sheet 16 rev. 1.1, 2012-12-03 tle4291 enable function 7 enable function 7.1 description enable function the tle4291 can be turned on or turned off via th e en input. with voltage levels higher than v en,high applied to the en input the device will be complete ly turned on. a volt age level lower than v en,low sets the device to low quiescent current mode. in this condition the device is turned off and is not functional. the enable input has an build in hysteresis to avoid toggling between on/off state, if signals with slow slope are applied to the input. 7.2 electrical character istics enable function electrical characteristics: enable function v i = 13.5v, t j = -40 c to +150 c, all voltages with respect to ground, direction of currents as shown in (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 7.2.1 enable low signal valid v en,low ??0.8v? 7.2.2 enable high signal valid v en,high 2??v v q settled 7.2.3 enable threshold hysteresis v en,hyst 30??mv? 7.2.4 enable input current i en ??2a v en = 5 v 7.2.5 enable internal pull-down resistor r en 34.56m ?
tle4291 reset function data sheet 17 rev. 1.1, 2012-12-03 8 reset function 8.1 description reset function the reset function provides several features: output undervoltage reset: an output undervoltage condition is indicated by setting t he reset output ?ro? to ?low?. this signal might be used to reset a microcontroller during low supply voltage. power-on reset delay time the power-on reset delay time t d,pwr-on allows a microcontroller and oscillator to start up. this delay time is the time period from exceeding the reset switching threshold un til the reset is released by switching the reset output ?ro? from ?low? to ?high?. the power-on reset delay time t d,pwr-on is defined by an external delay capacitor c d connected to pin ?d? which is charged up by the delay capacitor charge current i d,ch starting from v d = 0 v. in case a power-on reset delay time t d,pwr-on different from the value for c d = 100nf is required, the delay capacitor?s value can be derived fr om the specified value given in item 8.2.13 : c d = 100nf t d,pwr-on / t d,pwr-on,100nf (1) with ? t d,pwr-on : desired power-on reset delay time ? t d,pwr-on,100nf : power-on reset delay time specified in item 8.2.13 ? c d : delay capaci tor required. the formula is valid for c d 10nf. for precise timing calculations cons ider also the delay capacitor?s tolerance. reset reaction time in case the output voltage of the regulator drops below the output undervoltage lower reset threshold v rt,lo , the delay capacitor c d is discharged rapidly. once the delay capacito r?s voltage has reached the lower delay switching threshold v dst,lo , the reset output ?ro? will be set to ?low?. additionally to the delay capacitor discharge time t rr,d , an internal reaction time t rr,int applies. hence, the total reset reaction rime t rr,total becomes: t rr,total = t rr,int + t rr,d (2) with ? t rr,total : total reset reaction time ? t rr,int : internal reset re action time; see item 8.2.14 . ? t rr,d : delay capacitor discharge time. for a capacitor c d different from the value specified in item 8.2.15 , see typical performance graphs. reset output ?ro? the reset output ?ro? is an open collector output with an integrated pull-up resistor. in case a lower-ohmic ?ro? signal is desired, an external pull-up resistor to the ou tput ?q? can be connected. since the maximum ?ro? sink current is limited, the optional external resistor r ro,ext must not below as specified in item 8.2.7 .
data sheet 18 rev. 1.1, 2012-12-03 tle4291 reset function reset adjust function the undervoltage reset switching threshold can be adjuste d according to the application?s needs by connecting an external voltage divider ( r adj1 , r adj2 ) at pin ?radj?. for selecting the default threshold connect pin ?radj? to gnd. the reset adjustment range is given in item 8.2.5 . when dimensioning the volta ge divider, take into consid eration that there will be an add itional current constantly flowing through the resistors. with a voltage divider connected, the reset switching threshold v rt,new is calculated as follows v rt,lo,new = v radj,th ( r adj,1 + r adj,2 ) / r adj,2 (3) with ? v rt,lo,new : desired undervoltage reset switching threshold. ? r adj,1 , r adj,2 : resistors of the extern al voltage divider, see figure 6 . ? v radj,th : reset adjust switching threshold given in item 8.2.4 . figure 6 block diagram reset circuit gnd q i b lockdiagram _reseta djust .vsd or supply ro v dst int. supply i d,ch i dr , dsch v radj ,t h radj control d c d reset optional opti onal c q vdd micro- controller gnd r adj ,1 r adj ,2 r ro i ro i radj s r
tle4291 reset function data sheet 19 rev. 1.1, 2012-12-03 figure 7 timing diagram reset v i t v q t v rt,lo v rt,hi v ro timingdiagram _reset.vsd t v ro , low 1 v 1v t rr,total t d thermal shutdown input voltage dip t rr,total t d t d t < t rr,blank t d under- voltage spike at output over - load t rr,t ot al v rh v dst , lo v dst , hi t v d
data sheet 20 rev. 1.1, 2012-12-03 tle4291 reset function 8.2 electrical character istics reset function electrical characteristics: reset function v i = 13.5v, t j = -40 c to +150 c, all voltages with respect to ground, di rection of currents as shown in figure 6 (unless otherwise specified). pos. parameter symbol limit values unit conditions min. typ. max. output undervoltage r eset comparator default values (pin radj = gnd) 8.2.1 output undervoltage reset lower switching threshold v rt,lo 4.5 4.65 4.8 v v q decreasing radj = gnd 8.2.2 output undervoltage reset upper switching threshold v rt,hi 4.55 4.7 4.85 v v q increasing radj = gnd 8.2.3 output undervoltage reset headroom v rh 200 350 ? mv calculated value: v q - v rt,lo i q = 50 ma radj = gnd reset threshold adjustment 8.2.4 reset adjust lower switching threshold v radj,th 1.26 1.36 1.44 v 3.2 v v q < 5 v 8.2.5 reset adjustment range 1) 1) related parameter v rt is scaled linear when the reset switching threshold is modified. v rt,range 3.50 ? 4.65 v ? reset output ro 8.2.6 reset output low voltage v ro,low ? 0.1 0.4 v 1 v v q v rt,low ; no external r ro,ext 8.2.7 reset output external pull-up resistor to q r ro,ext 5.6 ? ? k 1 v v q v rt,low; v ro = 0.4 v 8.2.8 reset output internal pull-up resistor r ro 20 30 40 k internally connected to q reset delay timing 8.2.9 upper delay switching threshold v dst,hi ? 0.9 ? v ? 8.2.10 lower delay switching threshold v dst,lo ? 0.25 ? v ? 8.2.11 delay capacitor charge current i d,ch ? 6.5 ? a v d = 0.6 v 8.2.12 delay capacitor reset discharge current i dr,dsch ? 70 ? ma v d = 0.6 v 8.2.13 power-on reset delay time t d,pwr,on,100nf 8 13.5 18 ms calculated value; c d = 100 nf 2) 2) for programming a different delay and reset reaction time, see chapter 8.1 for calculation. 8.2.14 internal reset reaction time t rr,int ?9 15 s c d = 0 nf 8.2.15 delay capacitor discharge time t rr,d ?1.93 s c d = 100 nf 2) 8.2.16 total reset reaction time t rr,total ?1118 s calculated value: t rr,d,100nf + t rr,int ; c d = 100 nf 2)
tle4291 reset function data sheet 21 rev. 1.1, 2012-12-03 8.3 typical performance ch aracteristics reset function undervoltage reset switching threshold v rt,hi / v rt,lo vs. junction temperature t j power on reset delay time t rd versus delay capacitance c d power on reset delay time t rd versus junction temperature t j total reset reaction time t rr,total versus junction temperature t j 4.50 4.55 4.60 4.65 4.70 4.75 4.80 -40 0 40 80 120 160 t j [c] v rt [v] v rt, hi v rt, lo 01_vrt_tj.vsd 0 10 20 30 40 50 60 70 80 10 100 200 300 400 500 600 delay capacitance [nf] t d,pw ron [ms] t j = 25 c 02_tdpwron _delaycap .vsd 10 11 12 13 14 15 16 17 -40 0 40 80 120 160 t j [c] t d,pwron [ms] 03_tdpwron _tj.vsd c d = 100 nf 0 1 2 3 4 5 6 7 8 9 10 -40 0 40 80 120 160 t j [c] t rr,total [us] c d = 100nf 04_trr,total_tj.vsd
data sheet 22 rev. 1.1, 2012-12-03 tle4291 watchdog function 9 watchdog function 9.1 description the tle4291 features a programmable watchdog timing. the watchdog function monitors a microcontroller, including time base failures. in case of a missing rising edge within a certain pulse repetition time, the watchdog out put is set to ?low?. the programming of the expected watchdog pulse repetition time can be easily done by an external reset delay capacitor. the watchdog output ?wo? is separated from the reset ou tput ?ro?. hence, the watchd og output might be used as an interrupt signal for the microcontroller independent from the reset signal. it is possible to interconnect pin ?wo? and pin ?ro? in order to establish a wire-or function with a dominant low signal. figure 8 block diagram watchdog circuit watchdog output ?wo? the watchdog output ?wo? is an open co llector output with an integrated pull-up resistor. in case a lower-ohmic ?wo? signal is desired, an external pull-up resistor to the output ?q? can be connected. since the maximum ?wo? sink current is limited, the optional external resistor r wo,ext needs to be sized to comply with the watchdog output sink current (see item 9.2.8 and item 9.2.9 ). watchdog input ?wi? the watchdog is triggered by an positive edge at the wa tchdog input ?wi?. the signal is filtered by a bandpass filter and therefore its amplitude and sl ope has to comply wit h the specification 9.2.11 to 9.2.14 . for details on the test pulse applied, see figure 9 . gnd q i b lockdiagram_ w atchdog .vsd supply wo v dw int. supply i d,ch i dw ,dsch v dw , hi control d c d reset optional c q vdd micro- controller gnd edge detect wi i/o wi r wo s r 1 or i wo i q
tle4291 watchdog function data sheet 23 rev. 1.1, 2012-12-03 figure 9 test pulses watchdog input wi watchdog timing positive edges at the watchdog input pin ?wi? ar e expected within the watchdog trigger time frame t wi,tr , otherwise a low signal at pin ?wo? is generate d. if a watchdog low signal at pin ?wo? is generated, it remains low for t wd,lo . all watchdog timings are defined by charging and discharging the capacitor c d at pin ?d?. thus, the watchdog timing can be programmed by selecting c d . for timing details see also figure 10 . in case a watchdog trigger time period t wi,tr different from the value for c d = 100nf is required, the delay capacitor?s value can be derived fr om the specified value given in item 9.2.5 : c d = 100nf t wi,tr / t wi,tr,100nf (4) the watchdog output low time t wd,lo and the watchdog period t wd,p then becomes: t wd,lo = t wd,lo,100nf c d / 100nf (5) t wd,p = t wi,tr + t wd,lo (6) the formula is valid for c d 10nf. for precise timing calculations cons ider also the delay capacitor?s tolerance. figure 10 timing diagram watchdog v wi t v wi,lo v wi,hi t wi,hi d v wi / d t v wi v wi,lo v wi,hi t wi,hi t t wi,lo t wi,lo -d v wi / d t v wi t v wi,lo v wi,hi v wo timingdiagram _watchdog.vsd t v wo,low t wd,lo t wi,tr v dw , lo v dw , hi t v d t wd,lo t wi,p t wi,hi no positive v wi edge d v wi / d t outside spec t wi,lo
data sheet 24 rev. 1.1, 2012-12-03 tle4291 watchdog function 9.2 electrical character istics watchdog function electrical characteristics watchdog function v i = 13.5v, t j = -40 c to +150 c, all voltages with respect to ground, di rection of currents as shown in figure 8 (unless otherwise specified). pos. parameter symbol limit values unit conditions min. typ. max. watchdog timing 9.2.1 delay capacitor charge current i d ?6.5? a v d = 0.6 v 9.2.2 delay capacitor watchdog discharge current i dw,disch ?1.4? a v d = 0.6 v 9.2.3 upper watchdog timing threshold v dw,hi ?0.9?v? 9.2.4 lower watchdog timing threshold v dw,lo ?0.35?v? 9.2.5 watchdog trigger time t wi,tr,100nf 24 40 58 ms calculated value; c d = 100 nf 1) 9.2.6 watchdog output low time t wd,lo,100nf 6 8 12 ms calculated value; c d = 100 nf 1) ; v q > v rt,lo 9.2.7 watchdog period t wd,p,100nf 30 48 70 ms calculated value; t wi,tr,100nf + t wd,lo,100nf ; c d = 100 nf 1) 1) for programming a different watchdog timing, see chapter 9.1 . watchdog output wo 9.2.8 watchdog output low voltage v wo,low ?0.10.4v i wo = 1 ma; v wi = 0 v 9.2.9 watchdog output maximum sink current i wo,max 1.5 13 30 ma v wo = 0.8 v; v wi = 0 v 9.2.10 watchdog output internal pull-up resistor r wo 20 30 40 k ? watchdog input wi 9.2.11 watchdog input low signal valid v wi,lo ?? 0.8v 2) 2) for details on the test pulse applied, see figure 9 . 9.2.12 watchdog input high signal valid v wi,hi 2.6??v 2) 9.2.13 watchdog input high signal pulse length t wi,hi 0.5 ? ? s v wi v wi,hi 2) 9.2.14 watchdog input low signal pulse length (slewrate 1 v/ s) t wi,lo 2?? s v wi v wi,lo 2) ; d v wi /d t 1 v/ s 9.2.15 watchdog input low signal pulse length (slewrate 5 v/ s) t wi,lo 0.5 ? ? s v wi v wi,lo 2) ; d v wi /d t 5 v/ s v wi,hi 4 v
tle4291 watchdog function data sheet 25 rev. 1.1, 2012-12-03 9.3 typical performance characte ristics standard watchdog function watchdog trigger time t wi,tr versus delay capacitance c d watchdog trigger time t wi,tr versus junction temperature 01_twi_tr_delaycap.vsd 0 50 100 150 200 250 10 100 200 300 400 500 capacitance [nf] t wi,tr [ms] t j = 25 c 35 36 37 38 39 40 41 42 -40 0 40 80 120 160 t j [c] t wi,tri [ms] 02_twi_tr_tj.vsd
data sheet 26 rev. 1.1, 2012-12-03 tle4291 package outlines 10 package outlines figure 11 pg-ssop-14 ep green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-14-1,-2,-3-po v02 1 7 14 8 14 17 8 14x 0.25 ?.05 2) m 0.15 d c a-b 0.65 c stand off 0 ... 0.1 (1.45) 1.7 max. 0.08 c a b 4.9 ?.1 1) a-b c 0.1 2x 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion bottom view ?.2 3 ?.2 2.65 0.2 ?.2 d 6 m d 8x 0.64 ?.25 3.9 ?.1 1) 0.35 x 45? 0.1 cd +0.06 0.19 8 ? max. index marking exposed diepad for further information on packages, please visit our website: http://www.infineon.com/packages . dimensions in mm
tle4291 revision history data sheet 27 rev. 1.1, 2012-12-03 11 revision history revision date changes 1.1 2012-12-03 page 23 : figure 9 : definition in test pulses watchdog input wi extended with low signal pulse length. definition of frequency deleted according to the new specification of the watchdog in put signal with high and low time. page 23 : figure 10 : definition of watchdog input signal frequency deleted and definition for watchdog input low time added. page 24 : specification for ?watchdog input wi? corrected: specification for watchdog input low time as replacement for watchdog input signal frequency. slewrate specificatio n moved to condition for watchdog input low time. page 24 : 9.2.14 : specification of minimum watchdog input low time for slewrates 1 v/ s. page 24 : 9.2.15 : specification of minimum watchdog input low time for slewrates 5 v/ s. 1.0 2011-06-07 data sheet
edition 2012-12-03 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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